april 1998 4-135 mic3832/3833 micrel 4 features ? 15.9v startup, up to 21v operation (mic3832) 8.3v startup, up to 21v operation (mic3833) ? 9.8v undervoltage lockout (mic3832) 7.8v undervoltage lockout (mic3833) ? 0.5ma maximum startup current (40 m a typical) ? 17ma typical operating current ? 50ns maximum rise and fall times ? 30khz to 500khz rc oscillator ? voltage or current-mode control ? cycle-by-cycle current limit ? soft start function ? 5v 2% reference sources 20ma ? totem-pole output drive stages 1a peak output drive current ? 22v zener clamp on supply pin ? pwm latch eliminates false outputs from noise or ringing ? adjustable maximum duty-cycle limit ? 5mhz bandwidth error amplifier applications ? high-power, multiple-output, switched-mode power supplies and dc-to-dc converters ? current-fed, push-pull, switched-mode power supplies or dc-to-dc converters ? isolated high-voltage supplies ordering information part number temperature range package MIC3832BN C40 c to +85 c 16-pin plastic dip mic3832bwm C40 c to +85 c 16-pin wide soic mic3833bn C40 c to +85 c 16-pin plastic dip mic3833bwm C40 c to +85 c 16-pin wide soic general description the mic3832 and mic3833 are unique pwm controllers designed for current-fed, multiple-output or push-pull, switched-mode power supply applications. the mic3832/3 features uvlo (undervoltage lockout) with hysteresis, soft start with a programmable time constant, cycle-by-cycle current limiting, a pwm latch to prevent mul- tiple outputs due to noise or ringing, and front-edge blanking. current-fed topologies eliminate core saturation problems caused by shoot through (cross conduction) of push-pull circuits and reduce stress on the switching transistors. the mic3832/3 has one pwm stage capable of operating up to 500khz and two output stages, q and q, that operate at one-half of the system frequency at a fixed 50% duty cycle. the mic3832 uvlo circuit permits startup when the supply is above 15.9v and forces shutdown when the supply drops below 9.8v. the mic3833 starts up above 8.3v and shuts down below 7.8v. an internal 22v zener diode provides low power overvoltage protection. the three output stages are totem-pole drivers capable of 1a peak current to external power mosfets, bjts, or igbts. the q and q outputs have an intentional 50ns overlap (no dead time). mic3832/3833 current-fed pwm controllers not recommended for new designs pin configuration 1 14 2 3 4 5 6 7 13 12 10 9 11 gnd c t q v dd 5v ref ea ea + ea out r t sync cmr mdc/ss shdn nc pwm q 8 15 16 dip (n) or wide soic (wm)
mic3832/3833 micrel 4-136 april 1998 pin description pin number pin name pin function 1 gnd ground: use as single-point ground tie point. 2 pwm pwm output: variable duty-cycle totem pole output. 3 q switch (output): totem pole output. noninverting 50% duty cycle output (180 out-of-phase with q with no dead time). 4v dd supply voltage (input): clamped to 22v by internal zener diode. 5 5v ref 5v bandgap reference (output) 6 ea C inverting error amplifier input 7 ea + noninverting error amplifier input 8 ea out error amplifier output: connect to the appropriate feedback network to adjust the open loop gain or frequency response. 9 nc no connection: do not useleave open. 10 shdn overcurrent shutdown (input): >1 v disables outputs, >1.25v initiates soft- start restart. for cycle-by-cycle current limiting, even in voltage-mode control applications, connect to current sensor. if current sense is not used, connect to gnd. 11 mdc/ss maximum duty cycle/soft start (input): apply a dc voltage to adjust maxi- mum duty cycle (see chart). adjust soft start by adding capacitance to increase turn-on time during initial start up or restart after overcurrent shutdown. 12 cmr current mode ramp: feed point for a sample of inductor current when using current mode control. for voltage-mode control, connect directly to the c t pin. 13 sync synchronization (input): ac coupled input from an external master clock (reference) signal. if not used, leave unconnected. a high (>1.5v) resets the c t ramp. 14 r t oscillator timing resistor: connect 4k w minimum resistor to gnd. 15 c t oscillator timing capacitor: connect capacitor to gnd. see typical characteristics: discharge time graph for capacitor value. maximum oscillator frequency 1 2 discharge time = () 16 q switch (output): totem pole output. inverting 50% duty cycle output (180 out-of-phase with q with no deadtime).
april 1998 4-137 mic3832/3833 micrel 4 electrical characteristics (notes 2, 3) t a = C40 c to +85 c, v dd = 15v, f = 52khz unless otherwise specified. parameter conditions min typical max units reference section output voltage i o = 1ma, t a = 25 c 4.90 5.0 5.10 v input regulation v cc = 12v to 20v 5 20 mv output regulation i o = 1ma to 20ma 6 25 mv temperature stability C0.2 mv/ c total output variation 50 mv output noise voltage f = 10hz to 10khz, t a = 25 c50 m v long term stability t a = 125 c, 1000hrs. 5.0 mv output short circuit current v ref = 0 25 60 160 ma oscillator section frequency t a = 25 c, r t = 16k w , c t = 2.2nf 47 52 57 khz voltage stability v cc = 12v to 20v 0.5 % amplitude (c t ) 1.7 v p-p discharge current t a = 25 c 1 2.3 5 ma synchronization ac coupled 1.5 v error amplifier section input offset voltage C15 215mv input bias current 0.6 3.0 m a input offset current 0.1 1.0 m a open loop gain 1v < v o < 4v 60 82 db cmrr 1.5v < v cm < 4.5v 75 95 db psrr 12v < v dd < 20v 85 120 db output sink current v ea out = 1v 1.0 2.5 ma output source current v ea out = 4v C0.5 C1.3 ma output high voltage i ea out = C0.5ma 4.0 4.9 5.0 v output low voltage i ea out = 1ma 0.6 1.0 v soft start/max duty cycle section bias current C0.05 m a discharge current 13 ma duty cycle clamp accuracy 40 50 60 % operating ratings storage temperature range ................... C65 c to +150 c operating temperature range .................. C40 c to +85 c reference load current ............................................. 25ma supply voltage (v dd ): mic3832 ....................... 16v to 21v supply voltage (v dd ): mic3833 ...................... 7.6v to 21v oscillator frequency range ..................... 10khz to 500khz oscillator timing resistor ............................. 3k w to 100k w oscillator timing capacitor .............................. 1nf to 10nf absolute maximum ratings (note 1) supply voltage, v dd (continuous) ................................. 22v source/sink load current (peak) .................................... 1a maximum supply (zener) current .............................. 50ma junction temperature ............................................... 150 c lead temperature, soldering ....................... 260 c for 10s q ja plastic dip ....................................................... 130 c/w
mic3832/3833 micrel 4-138 april 1998 parameter conditions min typical max units current limit/shutdown section bias current C0.02 m a current limit threshold 0.9 1.0 1.1 v shutdown threshold 1.125 1.25 1.375 v delay to output 400 600 ns front edge blanking time 140 ns pwm comparator section bias current measured at cmr (pin 12) C2 C0.05 2 m a duty cycle range c = 2.2nf 0 85 % delay to output 300 500 ns output sections output low level i sink = 20ma 0.1 0.4 v i sink = 200ma 1.5 2.5 v output high level i source = 20ma 12.5 v i source = 200ma 12 13.1 v rise time c l = 1000pf 50 150 ns fall time c l = 1000pf 50 150 ns uvlo saturation i sink = 1ma 0.7 1.1 v q to q overlap q rising, q falling, 50% 50 ns q to q overlap q rising, q falling, 50% 50 ns undervoltage lockout section upper thresholdstartup mic3832 15.9 v mic3833 8.3 v lower thresholdoperating mic3832 9.8 v (shutdown) mic3833 7.8 v total standby current startup current 0.04 0.2 ma operating supply 17 ma v cc zener voltage i cc = 25ma 22 v note 1 absolute maximum ratings indicate limits beyond which damage to the device may occur. electrical specifications do not apply when operating the device beyond its specified operating ratings . note 2 minimum and maximum electrical characteristics are 100% tested at t a = 25 c and t a = 85 c, and 100% guaranteed over the entire range. typicals are characterized at 25 c and represent the most likely parametric norm. note 3 all pins esd protected to 2kv. test conditions: supply pin grounded; all other pins floating.
april 1998 4-139 mic3832/3833 micrel 4 typical characteristics 4.94 4.96 4.98 5.00 5.02 5.04 5.06 -40 0 40 80 120 160 reference voltage (v) junction temperature ( c) reference voltage vs. junction temperature 15.6 15.8 16.0 16.2 16.4 -40 0 40 80 120 160 under-voltage lockout (v) 9.2 9.4 9.6 9.8 10.0 -40 0 40 80 120 160 junction temperature ( c) mic3832 undervoltage lockout vs. junct. temp. on off 10 100 1000 1 10 100 frequency (hz) timing resistance (k w ) oscillator frequency vs. timing resistance 85pf 550pf 1.1nf 2.2nf 10.2nf note 4 0.1 1 10 110 timing capacitor discharge time ( m s) timing capacitor (nf) discharge time vs. timing capacitance -40 c 125 c 25 c 234568 0 1 2 3 4 5 -40 0 40 80 120 160 discharge current (ma) junction temperature ( c) oscillator discharge current vs. junct. temp. 0 10 20 30 40 50 60 70 80 90 100 012345 maximum duty cycle (%) mdc control voltage (v) voltage-mode max. duty cycle vs. mdc voltage note 5 0 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 output saturation voltage (v) output sink current (a) output saturation voltage vs. output sink current -55 c 125 c 25 c 0 1 2 3 0123456 current sense threshold (v) error amp output (v) current sense threshold vs. error amplifier output 25 c 125 c -55 c v ii = 1 v ii = 3 v ii = 2 -25 0 25 50 75 100 -180 -135 -90 -45 0 45 1x10 1 1x10 2 1x10 3 1x10 4 1x10 5 1x10 6 1x10 7 1x10 8 amplitude (db) phase ( ) frequency (hz) amplitude phase error amplifier open-loop frequency response 7.0 7.5 8.0 8.5 9.0 -40 0 40 80 120 160 reference voltage (v) junction temperature ( c) mic3833 undervoltage lockout vs. junct. temp. on off 0 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 output voltage drop (v) output source current (a) output voltage drop vs. output source current 125 c 25 c -55 c note 4: cmr (pin 12) connected to c t (pin 15). note 5: cmr (pin 12) connected to c t (pin 15). mdc voltage measured at mdc/ss (pin 11). c t = 1nf, r t = 10k w .
mic3832/3833 micrel 4-140 april 1998 v dd r t c t ea + ea out cmr mdc/ss shdn gnd sync ea 5v ref front edge blanking osc 1-shot 1.5v pwm mdc r s s r toggle ? 2 q pwm q ref pwm latch uvlo latch uvlo 21v v dd v dd v dd 1.25v 1.0v ea mic3832/3833 block diagram
april 1998 4-141 mic3832/3833 micrel 4 functional description refer to the block diagram and figure 5. the mic3832 and mic3833 are self-contained controllers, with a voltage reference, voltage-mode error amplifier; cur- rent-mode, maximum duty cycle, overcurrent, and shutdown comparators; and an undervoltage lockout circuit. three control loops are provided: voltage-mode through the error amplifier, current-mode through the pwm comparator, and overcurrent through the shutdown comparator. three totem- pole outputs provide up to 1a peak synchronized drive to external fets for current-fed push-pull or bridge transformer applications. undervoltage lockout (uvlo) undervoltage lockout (uvlo) requires that the input voltage rise above 15.9v (mic3832) or 8.3v (mic3833) before the startup circuit is energized. once operating, the controller will not shut down until the supply drops to 9.8v (mic3832) or 7.8v (mic3833). there is an internal 22v zener between v dd and ground for overvoltage clamping. zener current should be limited to less than 20ma. voltage reference (ref) the reference consists of a 5v bandgap reference internally trimmed to 2% accuracy. it provides an internal reference and can be used to supply up to 25ma to external circuits. oscillator (r t /c t ) the oscillator stage performs two functions. first, it provides a linear sawtooth waveform which is fed to the pwm com- parator in voltage-mode control. second, it toggles the flip- flop which provides the q and q outputs. the oscillator frequency is configured using an external timing resistor and capacitor. a nominal voltage of 3.6v appears on the r t pin; the resulting current is then mirrored through the c t pin which charges the timing capacitor and generates the linear ramp. it is important to select an appropriate capacitor. at high frequencies effective series resistance, effective series in- ductance, dielectric loss and dielectric absorption all affect frequency stability and accuracy. rf capacitors such as silver mica, glass, polystyrene, or cog ceramics are recom- mended. high k ceramics should not be used. front-edge blanking this feature provides a fixed delay time prior to current sensing becoming active. this prevents the overcurrent sensing function from being falsely tripped by initial system transients. timing is set to a nominal 140ns. error amplifier (ea) the error amplifier is an opamp with a low impedance output that is used to sense output conditions and provide a dc output based on those conditions to the pwm comparator. the output of this stage is brought out to allow tailoring of the closed loop gain or frequency response. the open loop gain of this stage is typically 95db. the inputs are diode clamped to each other. pwm comparator a sawtooth waveform is compared to the output of the error amplifier. the sawtooth is generally the oscillator waveform on c t in voltage-mode control systems. in current-mode control systems, it is often the inductor current waveform. both systems result in a square wave output which, after being nored with the mdc output (see below), is used to drive the main (pwm) output stage. pwm latch and output the pwm latch is reset by an oscillator rising cycle, turning the pwm output on if shdn or uvlo are inactive. the pwm comparator trips when the cmr rising ramp voltage exceeds the error amplifier output voltage, setting the pwm latch and terminating the pwm output, after a minimum time set by the front edge blanking one-shot. if the output voltage is below the setpoint, the pwm cycle is terminated at a maximum duty cycle set by the voltage on the mdc/ss pin. if the output voltage is above the setpoint, the error amplifier output is low, and the pwm cycle terminates after the minimum set by the front edge blanking one-shot. the pwm output is designed to source and sink 1a peak into 1,000 pf loads. the output is disabled when shdn is enabled. push-pull outputs (q and q) two push-pull outputs are provided, with their leading edge synchronized to alternating pwm rising ramp initiation. the two outputs are 180 out of phase, with a slight (50ns typ.) overlap. the push-pull outputs are designed to source and sink 1a peak into 1,000 pf loads. this peak current was chosen to provide the designer with the option of using bipolar, mosfet, or igbt switching elements. to minimize ringing on the output waveform, the series inductance seen by the drivers should be as low as possible. this can be accomplished by keeping the distance between the mic3832/ 3 and the switching elements as short as possible, or by using carbon composition resistors in series with the fet gates. the q and q outputs have a small overlap with no dead time. while advantageous to current-fed topologies, other topolo- gies may require slight modification to accommodate this overlap. the outputs are disabled when shdn is enabled. maximum duty cycle (mdc) this feature, which uses the same pin as soft start (mdc/ss), provides another method of limiting duty cycle. the voltage seen by this pin determines the maximum duty cycle that can be obtained from the pwm output. as this feature can vary by as much as 15% over temperature, it is not recommended that it be used in place of a well designed feedback loop. the voltage on mdc/ss, the inverting input of the mdc comparator, is compared to the voltage on cmr, with internal front edge blanking. for voltage-mode operation, refer to the graph, typical characteristics: voltage-mode max. duty cycle vs. mdc voltage. voltage-mode operation requires the timing ca- pacitor ramp, from c t , be connected directly to cmr.
mic3832/3833 micrel 4-142 april 1998 if a voltage-divided portion of the timing capacitor ramp (from c t ) is fed to cmr (to slope compensate for current-mode subharmonic oscillation, for example), the corresponding maximum duty cycle control voltage must be proportionally reduced to achieve the same duty cycle control. soft start this feature prevents damage due to large inrush currents generated upon initial application of system power or when the device attempts to restart after an overcurrent shutdown by the current limit function. when soft start is activated, the pwm comparator output duty cycle will increase slowly, with a time constant determined by the size of the external capacitor connected to mdc/ss. (timing is r th c, where r th is the thevenin equivalent resistance seen by this pin.) overcurrent sensing and shutdown overcurrent sensing and shutdown is accomplished via a current sense transformer or an external sense resistor connected from the switching element (power transistor) to ground. the current ramp is fed into the noninverting input of two sensing comparators (shdn). if the sensed voltage equals or exceeds 1.0v, the corresponding input to the logic gates is pulled low, and the pwm comparator output is overridden. this provides a current limited output. if 1.25v is exceeded, the other comparator is also tripped activating the soft start feature. application information voltage mode voltage mode control has a single feedback path, comparing the oscillator voltage ramp with the output of an error amplifier which is comparing a sample of the dc output voltage to a reference. the mic3832/3 may be operated in voltage mode by connecting c t directly to cmr. excessive current may be controlled indirectly by driving shdn. input voltage changes are sensed as output voltage changes, with delayed re- sponse. the esr (effective series resistance) of each output capacitor adds a pole, requiring a compensating zero or low- frequency roll-off in the error amplifier. loop gain varies with input voltage. current mode current-mode control samples the inductor current wave- form. it provides feedback from the output stage, limits peak switching transistor current, removes one pole (the lc filter pole) from the output, provides input voltage feedforward with good rejection of input line transients, and reduces the problem of core saturation. the cmr pin monitors the inductor current. current-mode control uses a current sense resistor or trans- former to provide a voltage ramp which is compared the output of an error amplifier/comparator which is comparing a sample of the dc output voltage to a reference. the mic3832/3 may be operated in current mode by connect- ing the current sample to the cmr pin. input voltage variations affect the inductor current slope, providing fast response. two feedback loops complicate circuit analysis. the error amplifier controls the output current, with a single pole from the output filter. multiple supplies may be connected in parallel without con- cern for current-hogging. slope compensation at duty cycles above 50% subharmonic oscillations may occur due to the negative resistance effect of the input, for example, current decreasing as input voltage increases. slope compensation, adding a portion of the oscillator ramp to the cmr pin, is used to remove this error. power circuit resonances may introduce instability due to output current variations. internal front edge blanking reduces the effect of leading edge inductive current spikes. push-pull cross conduction push-pull power stages have a problem when both power switches are on simultaneously, creating a short-circuit path from rail to rail. in order to eliminate this cross-conduction, or shoot-through, a dead-time is usually added at each transi- tion, allowing the energized switch to fully turn off before the opposite switch is energized. this dead time decreases efficiency as the available duty cycle time is reduced, making the input current larger than optimum for a given input voltage, with higher conduction losses. in a push-pull (forward) converter, an output inductor oper- ates like a buck converter to store and provide energy to the load and output capacitor during the deadtime. both output rectifier diodes are pulled into conduction by the output inductor during the deadtime, draining the magnetic field from the output transformer. at the start of each power cycle the energized input switch sees a virtual short-circuit in the transformer, until the opposite diode is pulled out of conduc- tion. current fed if a constant current source is added to the feedpoint of a push-pull power stage, no deadtime is needed between power cycles, since the switches may be designed to handle the limited cross-conduction current. no output inductor is needed to store energy during the deadtime, and the related problem of simultaneously conducting output rectifiers is eliminated. buck-derived current fed refer to figure 5. if a supply is designed to operate from a widely varying input voltage, such as the power line, a pwm step-down (buck) regulator may be used as the constant current input to the push-pull stage by omitting the customary output capacitor from the buck circuit. a bifilar wound pulse transformer is used to provide high-side drive to the pwm switch. a slightly overlapping drive is provided to the push-pull switches, so the output side of the buck inductor will swing toward ground during cross-conduction, limiting dissipated power.
april 1998 4-143 mic3832/3833 micrel 4 the push-pull cycles are synchronized to run at half of the pwm frequency, so a soft or zero voltage switch transition may be obtained, reducing spikes and emi. feeding a sample of the pwm oscillator ramp to the current-mode comparator along with the input current sample allows slope compensation to be obtained for pwm duty cycles above 50%, preventing subharmonic oscillation at low input volt- ages. boost-derived current fed if a regulator is designed to run at higher push-pull voltage than the input line voltage, a step-up (boost) pwm regulator, with an inductor switched to ground, minus the normal output capacitor, will provide a current limited input to the push-pull stage. in this configuration all three power switches may be operated low-side, simplifying their drive circuitry. an input fuse is needed to guard against short-circuits since there is no high-side series switch. construction hints careful prototyping techniques are required to prevent oscil- lations. traditional solderless breadboards are a source of noise, and should be avoided. use double-sided, copper- clad boards with a large area used as a single-point ground plane. all timing and loop compensation capacitors and resistors should be star connected to gnd (ground). wire lengths along the high-current path should be kept as short as possible, with appropriate wire gauges being used. do not socket the switching transistors as this can add to the voltage drop and power losses. current-fed push-pull smps figure 3 illustrates this basic topology, a standard push-pull configuration where the center tap of the primary is fed with an inductor current instead of a voltage. this constant current reduces cross conduction and catastrophic transformer core saturation. push-pull topologies are often used in 100w and larger power supplies as they allow more efficient use of the transformer. the entire range of the b-h curve is used in a push-pull supply, so a transformer that is one-half the size of a transformer used in a single-ended, forward-mode topology can be used. this topology can be extended to a full bridge where the two 50% duty cycle stages would be used to drive two mosfets each, one for each half of the bridge. l d1 s1 s2 s3 50% 50% duty cycle control figure 3: current-fed push-pull topology current-fed multiple-output smps figure 4 illustrates this topology. the absence of output inductors improves cross-regulation and simplifies the con- struction of isolated or high-voltage output supplies. l d1 s1 duty cycle control additional outputs s2 s3 50% 50% figure 4: current-fed multiple-output topology
mic3832/3833 micrel 4-144 april 1998 magnetics design t1 : magnetics inc # 41303 C tc, p material, primary = 26 turns 30 gauge wire, secondary = 26 turns 30 gauge wire t2: seimens efd25, n87 material. primary = 20 turns 20 gauge wire, secondary = 10 turns trifilar wound 20 gauge wire. both are center tapped. l1: seimens efd20, n87 material. 13 turns 20 gauge wire. gap for 20 m h 100khz 100w current-fed converter refer to figure 5. a 5v, 20a dc-to-dc converter uses the current-fed, push-pull configuration for increased safety and reduced size and transformer core area. the input is an unregulated 14v to 32vdc supply. an mic2951 low-dropout regulator supplies 12v to the mic3833. the main pwm switching element is an irf540, with gate drive provided by transformer t1. the two 50% duty cycle outputs each drive an irf540 directly, which in turn drive respective sides of t2s center tapped primary. the 1n6291a transzorb is used to protect the mosfets from spikes. current-mode control simplifies the stability analysis, with the 0.2 w , 5w resistor being used as the sensing element. as the maximum duty cycle at light loads is greater than 50%, the well characterized problem of subharmonic oscillations found when using current-mode control was evident. a ramp, introduced at the sensing element, provides slope compen- sation. the 10k w and 470k w divider from the oscillator (ramp source) to the sensing element provides the proper slope. a large resistor value from c t to cmr makes buffering unnec- essary. front-edge blanking eliminates the need for a filter network around the sensing element and decreases the possibility of turn-on transients that cause system instabilities. four inexpensive output capacitors in parallel reduce esr to an acceptable level of 80m w without adding too much size or cost. error amplifier compensation uses a simple lead-lag network. with current-mode control there is no need to compensate for the lc filter pole. soft start is implemented to allow slow turn-on in the event of a short circuit. all magnetics were chosen to minimize losses at 100 khz. t2 and l1 are wound using siemens n87 material and t1 using magnetics inc.s p-type material. t2 and l1 use siemens efd core and bobbin assemblies which are designed to reduce the height/form factor of the finished supply. t1 is a bifilar-wound toroid used as a 200khz pulse transformer. t2 is not gapped, since a push-pull transformer has a minimum dc current component, being a forward converter. 1 v out 2 sense 3 shdn 4 gnd fb 7 v in 8 5v tap 6 error 5 mic2951 887k w 1% 102k w 1% 3.3? 12v 100pf 3.3? 1/2 mbr2535ct 2:1 1/2 mbr2535ct irf540 irf540 20v 1n968 14?2v 20? irf540 39k w 39k w 220? 16v 220? 16v 0.01? cer 0.1? mylar mic3833 1 gnd 2 pwm 3 q 4 v dd 5 5v ref 6 ea 7 ea + 8 ea out nc 9 shdn 10 mdc/ss 11 c t 15 q 16 r t 14 sync 13 cmr 12 5.1 k w 5.1k w .01? 200k w 2.2nf 10k w 2nf 0.2 w 5w t2 0.1? 10 w 0.1? t1 l1 10k w 470k w mur1605ct 1n6291a 1n6291a 1:1 +5v 20a 100 w 68k 68k 1? 2000 ? figure 5: 100w current-fed, push-pull dc-to-dc converter (efficiency ~75%)
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